1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device capable of performing a stress test in which a plurality of word lines are activated at a time.
2. Description of Related Art
Various operation tests are performed during manufacturing stages of semiconductor devices such as a DRAM (Dynamic Random Access Memory). For example, in a wafer state, a test is performed to detect defective addresses, and after packaging, a screening test is performed to exclude chips that do not operate properly. One of such operation tests includes a stress test. The stress test mainly performed in the wafer state. In the stress test, test data are written to each memory cell, and electrical stress is given to each memory cell. Then, a determination is made as to whether the test data subsequently read have been changed or not.
In the stress test, a method for shortening a test time is known, in which the stress is given at the same time by a plurality of word lines activated at a time. For example, Japanese Patent Application Laid-Open No. 2001-143497 discloses “all word line activation test mode”. The stress test can be performed in a shorter time by increasing the number of word lines activated at a time, but a driver circuit for driving the word lines and a power supply circuit for supplying an operation voltage to the driver circuit are designed for normal operation, and therefore it is difficult to activate so many word lines at a time.